1. Field of the Invention
This invention relates to integrated circuit fabrication and, more particularly, to a method for reducing defects associated with deposition processes.
2. Description of the Relevant Art
Fabrication of a metal-oxide-semiconductor (MOS) integrated circuit (IC) involves numerous processing steps. A gate dielectric, typically formed from silicon dioxide ("oxide"), is formed on a semiconductor substrate which is doped with either n-type or p-type impurities. For each MOS field effect transistor (MOSFET) being formed, a gate conductor is formed over the gate dielectric, and dopant impurities are introduced into the substrate to form a source and drain. Such transistors are connected to each other and to terminals of the completed integrated circuit using conductive interconnect lines. Typically, multiple levels of interconnect are needed to provide the connections necessary for a modem, high-transistor-density IC.
Many of the processing steps mentioned above involve deposition of a material layer onto a semiconductor topography (semiconductor substrate with overlying layers and structures). For example, a gate conductor is typically patterned from a polysilicon layer deposited using chemical vapor deposition (CVD). Interlevel dielectrics, which insulate layers of interconnect from each other and from underlying devices, are also generally deposited using CVD. Interconnect formation often involves deposition of metal films by either CVD or by physical vapor deposition (PVD) methods, such as evaporation or sputtering. As is partially illustrated by these examples, effective deposition processes are critical to the success of integrated circuit fabrication.
A pervasive trend in modern integrated circuit manufacture is to produce transistors having feature sizes as small as possible. Many modem processes employ features, such as gate conductors and interconnects, which have less than 1.0 .mu.m critical dimension. As feature size decreases, the sizes of the resulting transistors as well as those of the interconnects between transistors also decrease. Fabrication of smaller transistors allows more transistors to be placed on a single monolithic substrate, thereby allowing relatively large circuit systems to be incorporated on a single, relatively small die area.
This trend toward reduced feature sizes imposes severe demands on many aspects of IC fabrication, including deposition processes. For example, reduction of device and interconnect dimensions may result in increased electric fields within the circuit (unless operating voltages are decreased by a corresponding amount). Increased electric fields require increased uniformity of layer thickness, composition, and structural quality in order to prevent local breakdown of or capacitive coupling through a deposited layer. Furthermore, decreased dimensions increase the probability that a localized defect such as a pinhole or a defect associated with a particle will be significantly detrimental to circuit operation. As an example, a particle landing on the surface of a semiconductor topography near the beginning of a metal deposition process may result in a lack of metal adhesion in the immediate vicinity of the particle. If the particle is included within a metal interconnect, a substantial portion of the width of the interconnect at the location of the particle could be rendered nonconductive. This effective narrowing of the interconnect at the location of the particle may increase the interconnect resistance at that location, and thereby result in excess heating as current flows through the high-resistance portion. Such heating may ultimately cause interconnect failure and render a circuit inoperative.
The importance of high-quality, high-uniformity deposited layers to continued improvement in IC performance has motivated substantial effort by IC manufacturers, process equipment manufacturers, and university researchers toward improving deposition process reliability. Extensive experimentation and computer modeling have been employed in identifying sources of defects and nonuniformity in deposited layers. Deposition reactor designs and deposition conditions and sequences have been optimized with the goal of eliminating these sources of defects and nonuniformity.
Despite the above-described efforts, some defects are present in typical deposited films. Moreover, some of the observed defects do not appear to be associated with controllable variables, and are therefore believed to be associated with inconsistencies in deposition equipment operation. It would therefore be desirable to develop a method for reducing densities of defects associated with process equipment inconsistencies. Such a method could also improve wafer-to-wafer consistency of deposited layers.